An analog memory device uses a number of different amplitude levels to store more than one bit in a single memory cell. The amplitude level stored in a particular cell corresponds to one of several multi-bit binary values. Conventional analog memory cells do not utilize coding and instead generally use 2.sup.n voltage levels to store n bits of information. A multi-bit binary value is stored in the cell by storing a voltage level which falls within a range corresponding to that level. For example, a three-bit binary value may be stored in a single cell by storing a particular one of eight voltage levels used to represent one of the eight possible three-bit values.
A significant problem in conventional analog memory devices is that the readout of the voltage level stored in a particular cell is generally corrupted by noise. The noise may cause a stored voltage level falling within a given voltage range to be misread as falling within another voltage range. As a result, conversion of the corrupted readout voltage to a multi-bit binary value may produce the incorrect value. The susceptibility of an analog memory cell to this type of noise-induced readout error generally depends on the size of the voltage ranges assigned to each multi-bit binary value. Since the memory cells are often constrained in practice to operate with commonly-available power supplies, the stored voltage level is typically restricted to be no larger than a certain maximum value. The need to provide an adequate voltage range for each multi-bit binary value in order to avoid noise-induced readout errors, coupled with the practical limitation on maximum cell voltage, places a severe constraint on the number of bits which can be stored in an analog memory cell, and thus on the storage capacity of a conventional analog memory device.
It is therefore apparent that a need exists for a technique which can increase the number of bits which can be stored in a given multi-bit memory cell, or alternatively provide improved readout reliability for a fixed number of stored bits per cell, without increasing the maximum stored voltage supported by the cell.